The present invention relates to a method for producing phase masks during an automated process of generating a layout of an integrated circuit.
A main object when generating a layout of integrated circuits is always to accommodate as many circuit elements as possible on as small an area as possible in order to increase the speed at which the integrated circuits operate. At the same time costs are reduced, since costs depend to a considerable extent on the area of the integrated circuit. However, at the same time, specific technology-dependent minimum separations or spacing distances must be maintained between different conductive areas on the integrated circuit. These conductive areas are normally in the form of a polygon.
The use of phase masks in the manufacture of integrated circuits allows the chip designer to place layout polygons, in other words conductive areas on a specific plane in the integrated circuit, closer to one another than polygons having the same phase, which are normally referred to as polygons xe2x80x9cof the same color.xe2x80x9d For simplicity, the polygons in a phase mask are regarded as having different colors for respective phases.
In order to minimize the area of the integrated circuit, it is thus worthwhile to plan or select the coloring of the polygons, that is to say the phase allocation, such that (at least in areas in which the relevant mask plane is critical for area consumption), as far as possible, only polygons xe2x80x9cof different colorxe2x80x9d, that is to say polygons of different phases, are adjacent.
In the prior art, little use has so far been made of this potential for saving layout areas. Several methods, which color the polygons xe2x80x9calternatelyxe2x80x9d with regard to their two-dimensional extent, are used. Manual optimization processes can also be carried out, of course, for relatively small layout blocks.
The prior art on which the present application is based is described in the book xe2x80x9cLeaf cell and hierarchical compaction techniquesxe2x80x9d by Cyrus Bamji and Ravi Varadarajan, Boston, Kluwer Academic Publishers, 1997. This book provides a good overview of the most important methods and latest developments in the field of layout compacting.
Prior art methods which are related to the method according to the invention can be found in the article xe2x80x9cMethod of Designing Phase-Shifting Masks Utilizing a Compactorxe2x80x9d by K. Ooi, K. Koyama and M. Kiryu, Japanese Journal of Applied Physics, Volume 33, pages 6774-6778, 1994. Kazuko et al. integrate the phase allocation and layout compacting in a joint overall sequence. However, the phase masks are not generated directly during the compacting process, so that it is impossible to find the optimum allocation with regard to the area optimization result.
A further related prior art method can be found in the article xe2x80x9cInsertion of Jog Series in Layout Compactionxe2x80x9d by W. L. Schiele, Th. Krueger and M. C. Utesch, in the journal xe2x80x9cIntegrationxe2x80x9d, Volume 16, No. 2, pages 149-162, 1993. This article describes a method for introducing bends or jog points. The bending of lines or introduction of jog points in the layout can lead to a considerable reduction in area. The method described optimizes a graph, to which a longest path algorithm has previously been applied.
Published, Non-Prosecuted German Patent Application DE 196 25 894 A1 describes a method for producing photo masks, in which optical proximity effects are corrected by using a predetermined correction method to correct scanning data which are produced on the basis of mask data received from outside. The corrected scanning data are used to control a pattern exposure process for producing the pattern of a photo mask.
According to Published, Non-Prosecuted German Patent Application DE 196 42 050 A1, the packing density of a circuit is increased by using a phase-shifting mask which is formed of alternately configured phase shifters.
It is accordingly an object of the invention to provide a method of producing phase masks which overcomes the above-mentioned disadvantages of the heretofore-known methods of this general type and which achieves an optimum allocation of the phases to the individual polygons.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of producing phase masks for automatically generating a layout for an integrated circuit, which includes:
compacting a layout of an integrated circuit by processing a distance graph;
allocating a respective phase to at least some of a plurality of polygons in the layout for generating a phase mask; and performing the allocating step during the processing of the distance graph.
In other words, the object of the invention is achieved in that the allocation takes place at least partially during the processing of the distance graph, that is to say at the same point in the compacting algorithm at which the jog points or the bending of lines is introduced according to the prior art from Schiele et al. According to the invention, the phase allocation can in this case be used as an alternative to or in addition to the introduction of bends or jog points.
It is particularly preferable in this case if the allocation of at least some of the polygons is carried out during the course of the longest path algorithm.
In accordance with another mode of the invention, the respective phase is allocated to given ones of the polygons having no allocated phase yet, if a longest path can be further shortened with the longest path algorithm.
It is particularly preferred, that polygons are allocated different phases only when these polygons have already achieved the minimum separation or distance between polygons of the same phase.
These features of the invention make sure that limitations in the design options, which would later prevent an optimum allocation, are not introduced prematurely by an unnecessarily early definition of the phase of the individual polygons.
It is therefore particularly preferable for some of the polygons to be allocated the phases only in later steps.
Some of the polygons are preferably allocated a phase only after the automatic jog point generation.
It is furthermore preferable for some of the polygons to be allocated a phase only in later compacting steps, for example during the alternate one-dimensional compacting in the X and Y directions.
Finally, it may be advantageous for some of the polygons to be allocated a phase only in an independent method separate from the layout compacting.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method of producing phase masks for automatically generating a layout for an integrated circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments.